A bus is a set of hardware lines used for data transfer among the components of a computer system. A bus is essentially a shared highway that connects different parts of the system--including the microprocessor, memory, and input/output ("I/O") ports--and enables them to transfer information. Typical buses have been designed so that one group of lines carries data while another carries the addresses where specific data can be found, and yet other lines carry control signals to insure that the different parts of the system use the bus without conflict. In contrast to this configuration, some computer systems utilize a multiplexed bus wherein the same lines of the bus carry both address and data information in a time domain multiplexed arrangement (i.e., address and data information are sent at different intervals).
A data processing system utilizing a multiplexed bus may encounter bus contention problems, wherein two different devices coupled to the bus, such as the microprocessor ("CPU") and an external memory, may simultaneously attempt to utilize the multiplexed bus (e.g., the CPU and the memory may both be attempting to transmit address and/or data information onto the multiplexed bus). Such a bus contention problem may readily occur after a read bus cycle. (A bus cycle is defined herein as the amount of time required for an "operation," such as the transfer of data during a read or write operation. "Read bus cycle" and "write bus cycle" are sometimes referred to herein as "read cycle" and "write cycle," respectively.) During a typical read bus cycle, the CPU has first transmitted the address of the data to be read from an external device (e.g., such as an external memory or an I/O module) to that same device. In response to receipt of this address, the memory or I/O module will then retrieve the requested data and drive the data to the CPU via the multiplexed bus. After completion of the transmission of the data, the memory or I/O module must tri-state the data bus conductors subsequent to the data phase of the cycle before the next address phase can begin (i.e., the memory device or I/O module must deselect, or release, the bus so that the CPU can utilize it to drive the next address). Note that the terms "tri-state" and "high impedance" will be used interchangeably herein to describe one or more bus conductors (lines) that have been placed in a high impedance state.
The foregoing problem is a result of external memories and I/O modules requiring long, and sometimes indeterminable, periods for deselecting the bus after transmitting read data onto the bus. The result is that the bus interface unit on the CPU is uncertain as to when it may drive another address onto the bus. This problem is exacerbated when the designers of the CPU are not aware of the type and/or manufacturer of the memory and/or I/O modules to be coupled to the CPU via the bus. In other words, it may be desirous to completely design the CPU and its resident bus interface unit without requiring knowledge of tri-state periods required by devices to be coupled to the CPU at a later time.
The prior art has dealt with the foregoing problem in several ways. One solution that has been implemented in previous systems is to drive the next address after a read cycle on the falling edge of the clock cycle ("clock cycle" and "clock" both refer to one clock cycle herein) subsequent to the read cycle. However, this solution is essentially inadequate and unreliable for bus frequencies above 20 MHz, since the half clock cycle may not be enough time for the bus device to deselect the bus and tri-state.
A second solution is to delay the next address phase of a bus cycle for a full clock cycle to allow the external memory or I/O module to deselect the bus. Essentially, this solution is to always insert one or more idle clock cycles before driving an address. A problem with this solution is that it results in a slower implementation and reduced utilization of the bus, thus decreasing the performance of the overall system. Another problem with the foregoing solution is that an idle clock cycle is not required to be inserted after a write bus cycle, since the bus interface unit of the CPU is in control of the timing of the write cycle, and thus knows when the write cycle ends and when it may transmit another address for the next read or write bus cycle.
A third solution is to require acknowledgment cycles after each address and data phase. Again, such a solution requires extra clock cycles, thereby decreasing the performance of the overall computer system.
A fourth solution is to provide for programming of required idle time after all bus cycles during the boot up of the computer system, wherein the bus interface unit is programmed with a specified idle time that pertains to the particular external memory or I/O module coupled to the bus. Such a solution is not practicable for the designer of the CPU when particulars of memory devices and I/O modules to be coupled to the CPU are not known at the time of manufacturing.
As a result of the foregoing, what is needed in the art is a technique for inserting idle clock cycles at appropriate times onto a multiplexed bus in order to alleviate bus contention problems, but not degrade the performance of the bus more than is necessary.